The Ridiculously Nerdy Intel Bet That Could Rake in Billions | EUROtoday

It’s nonetheless an especially difficult proposition. “Packaging is not as easy as saying, ‘I want to run 100,000 wafers per month,’” says Jim McGregor, a longtime chip business analyst and the founding father of Tirias Research, referring to a steady movement of chips in numerous levels of manufacturing. “It really comes down to whether Intel’s [packaging] fabs can make deals. If we see them expanding those operations more, that’s an indicator that they have.”

Last month, Anwar Ibrahim, the prime minister of Malaysia, revealed in a put up on Facebook that Intel is increasing its Malaysian chip-making amenities, which had been first established again within the Nineteen Seventies. Ibrahim stated the top of Intel’s Foundry, Naga Chandrasekaran, had “outlined plans to commence the first phase” of enlargement, which would come with superior packaging.

“I welcome Intel’s decision to begin operations for the complex later this year,” a translated model of Ibrahim’s put up learn. An Intel spokesperson, John Hipsher, confirmed that it’s constructing out further chip meeting and check capability in Penang, “amid rising global demand for Intel Foundry packaging solutions.”

Package Store

According to Chandrasekaran, who took over Intel’s Foundry operations in 2025 and spoke completely with WIRED throughout the reporting of this story, the time period “advanced packaging” itself didn’t exist a decade in the past.

Chips have at all times required some type of integration of transistors and capacitors, which management and retailer power. For a very long time the semiconductor business was targeted on miniaturization, or, shrinking the scale of elements on chips. As the world started demanding extra from its computer systems within the 2010s, chips began to get much more dense with processing models, high-bandwidth reminiscence, and the entire vital connective components. Eventually, chipmakers began to take a system-in-packages or package-on-package strategy, by which a number of elements had been stacked on high of each other so as to squeeze extra energy and reminiscence out of the identical floor house. 2D stacking gave option to 3D stacking.

TSMC, the world’s main semiconductor producer, started providing packaging applied sciences like CoWoS (chip on wafer on substrate) and, later, SoIC (system on built-in chip) to clients. Essentially, the pitch was that TSMC would deal with not simply the entrance finish of chip-making—the wafer half—but additionally the again finish, the place the entire chip tech could be packaged collectively.

Intel had ceded its chip manufacturing result in TSMC at this level, however continued to spend money on packaging. In 2017 it launched a course of referred to as EMIB, or embedded multi-die interconnect bridge, which was distinctive as a result of it shrunk the precise connections, or bridges, between the elements within the chip package deal. In 2019, it launched Foveros, a complicated die-stacking course of. The firm’s subsequent packaging development was an even bigger leap: EMIB-T.

Announced final May, EMIB-T guarantees to enhance energy effectivity and sign integrity between all of the elements on the chips. One former Intel worker with direct information of the corporate’s packaging efforts tells WIRED that Intel’s EMIB and EMIB-T are designed to be a extra “surgical” method of packaging chips than TSMC’s strategy. Like most chip developments, that is imagined to be extra energy environment friendly, save house, and, ideally, save clients cash in the long termThe firm says EMIB-T will roll out in fabs this 12 months.